In dynamic RAM memories, the information to be stored by a memory cell is generally held on a capacitor known as a storage capacitor. In system-on-chip applications in a pure logic technology, storage capacitors are often created by means of the gate capacity of an MOS transistor (e.g. a MoSyS-1T-SRAM, a 1T-cell of a static random access memory from MoSys Inc.) or by means of connection in parallel of gate and diffusion capacity (e.g. IFX-2T concept, a 2T-cell concept from Infineon).
Because of the leakage currents, a storage capacitor slowly loses its charge which can lead to the loss of the information stored on the capacitor. In order to counter this, in microelectronic circuits the charge of all storage capacitors is refreshed again at certain intervals, so that the information is retained. This interval depends, amongst other things, on the size of the memory capacity.
As a result of increasing integration the leakage currents in the abovementioned system-on-chip applications are becoming ever greater and new leakage current sources such as the gate leakage currents are arising due to the increasingly thin oxide coatings. The total memory capacity is also becoming smaller.
An object of the invention is to provide a storage capacitor with the highest possible memory capacity and the lowest possible surface area usage, which in particular in a pure logic technology can be created without additional, and thus more expensive, process steps.